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| TECHNICAL DATA IN74HCT244A Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS The IN74HCT244A is identical in pinout to the LS/ALS244. The device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. The IN74HCT244A is an octal noninverting buffer/line driver/line receiver designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has non-inverted outputs and two active-low output enables. * TTL/NMOS-Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A ORDERING INFORMATION IN74HCT244AN Plastic IN74HCT244ADW SOIC IN74HCT244AZ Chip TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Enable A, Enable B PIN 20=VCC PIN 10 = GND L L H A,B L H X Outputs YA,YB L H Z X=don't care;Z = high impedance INTEGRAL 1 IN74HCT244A MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) ** Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 35 75 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74HCT244A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Symbol Parameter Test Conditions VCC V VIH VIL VOH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT= VCC-0.1 V IOUT 20 A VOUT=0.1 V IOUT 20 A VIN=VIH IOUT 20 A VIN=VIH IOUT 6.0 mA VOL Maximum Low-Level Output Voltage VIN= VIL IOUT 20 A VIN= VIL IOUT 6.0 mA IIH Minimum High-Level Input Leakage Current Maximum Low-Level Input Leakage Current Minimum High-Level Three-State Leakage Current Maximum Low-Level Three-State Leakage Current Maximum Quiescent Supply Current per Package) Additional Quiescent Supply Current VIN=VCC 4.5 5.5 0.26 0.1 0.33 1.0 0.4 1.0 A 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 V V V V Unit IIL VIN=GND 5.5 -0.1 -1.0 -1.0 A IOZH VIN(01) =VIH VIN(19) =VIH VIN =VNN (on other outputs) VOUT=VCC VIN(01) =VIH VIN(19) =VIH VIN =VNN (on other outputs) VOUT=GND VIL=GND VIN=VCC IOUT=0 A VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0A 5.5 0.5 5.0 10.0 A IOZL 5.5 -0.5 -5.0 -10.0 A ICC 5.5 4.0 40 160 A ICC -55C 25C to 125C mA 5.5 2.9 2.4 NOTE: Total Supply Current = ICC + ICC. INTEGRAL 3 IN74HCT244A AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Symbol Parameter Test Conditions VCC A Guaranteed Limit 25 C to -55C 20 85C 125 C 30 ns Unit tPLH, t PHL Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 2) VCC=5 V10% VIL=0 V VIH=3 V tLH=t HL=6 ns CL=50 pF VCC=5 V10% VIL=0 V VIH=3 V tLH=t HL=6 ns CL=50 pF VCC=5 V10% VIL=0 V VIH=3 V tLH=t HL=6 ns CL=50 pF VCC=5 V10% VIL=0 V VIH=3 V tLH=t HL=6 ns CL=50 pF VCC=5 V10% VCC=5 V10% 5.0 25 tPLZ, t PHZ Maximum Propagation Delay , Output Enable to YA or YB (Figures 1 and 2) 5.0 26 33 39 ns tPZL, t PZH Maximum Propagation Delay , Output Enable to YA or YB (Figures 1 and 2) 5.0 22 28 33 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 2) 5.0 12 15 18 ns CIN COUT Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) 5.0 5.0 10 15 10 15 10 15 pF pF Power Dissipation Capacitance (Per Enabled Output) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25C,VCC=5.0 V 55 pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms INTEGRAL 4 IN74HCT244A Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/8 of the Device) INTEGRAL 5 IN74HCT244A CHIP PAD DIAGRAM IZ74HCT244A Pad size 0.106 x 0.106 mm (Pad size is given as per passivation layer) Thickness of chip 0,460,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Symbol ENABLE A A1 YB4 A2 YB3 A3 YB2 A4 YB1 GND B1 YA4 B2 YA3 B3 YA2 B4 YA1 ENABLE B Vcc X 0.152 0.152 0.300 0.470 0.868 1.068 1.330 1.709 1.729 1.729 1.699 1.729 1.719 1.301 1.062 0.758 0.468 0.142 0.152 0.152 Y 0.636 0.396 0.142 0.152 0.132 0.152 0.132 0.142 0.578 0.812 1.149 1.438 1.804 1.824 1.804 1.824 1.804 1.662 1.489 1.005 INTEGRAL 6 |
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